Technology

IBM Unveils World’s 1st 0.7nm Chip Technology With Nanostack Design

The chip enables continued improvements in performance and energy efficiency at atomic-scale dimensions, it added. It packs nearly 100 billion transistors onto a device roughly the size of a fingernail, almost doubling the transistor density of its 2 nm chip technology unveiled in 2021.

IBM Unveils World’s 1st 0.7nm Chip Technology With Nanostack Design
IBM 0.7nm Chip (Photo Credits" IBM)
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New Delhi, June 25: US-based technology giant IBM on Thursday unveiled what it described as the world's first sub-1 nanometre (nm) chip technology, a major breakthrough for the semiconductor industry as it approaches the physical limits of conventional chip scaling.

The new chip is built on a 0.7 nm, or 7-angstrom, process node and features a novel three-dimensional transistor architecture called nanostack, according to the company. The chip enables continued improvements in performance and energy efficiency at atomic-scale dimensions, it added. It packs nearly 100 billion transistors onto a device roughly the size of a fingernail, almost doubling the transistor density of its 2 nm chip technology unveiled in 2021. OpenAI Unveils Jalapeno Chip for Next-Generation AI Inference.

The new technology is projected to deliver up to 50 per cent higher performance or 70 per cent greater energy efficiency compared to its 2 nm node chips, the company said. The advancement is expected to support demanding applications such as generative AI, cloud infrastructure and next-generation electronic devices.

"IBM's latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometre era to the scale of atoms," said Jay Gambetta, Director of IBM Research and IBM Fellow. The company said its nanostack architecture vertically stacks and staggers transistors, allowing more components to be packed onto a chip while enabling different materials to be optimised independently for performance and power efficiency.

Meanwhile, IBM researchers demonstrated that the architecture can significantly improve SRAM scaling, helping chip designers build more efficient processors capable of handling high-bandwidth AI workloads. The company said it expects the earliest commercial adoption of the technology within the next five years. Odisha: Intel and 3D Glass Solutions Sign MOU to Explore Advanced Semiconductor Packaging Facility in State.

In addition, the research was conducted at IBM's semiconductor research facility in Albany, New York, in collaboration with industry partners including ASML, Lam Research, Tokyo Electron and SCREEN Semiconductor Solutions.

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