India News | IIT Delhi Researchers Develop First Indigenously Designed Micro-Graphics Processing Unit
Get latest articles and stories on India at LatestLY. The project, led by M Tech students Nammi Akash and M Ravi Teja under the guidance of Jayadeva and Kaushik Saha from the Electrical Engineering Department, IIT Delhi, has demonstrated programmable graphics rendering using a custom floating-point GPU engine implemented entirely in Register Transfer Language (RTL) and mapped to a Spartan-7 Field Programmable Gate Array (FPGA) platform.
New Delhi [India], September 24 (ANI): Graphics Processing Units (GPUs) are widely used in modern hardware, including in AI and Machine Learning engines.
Currently, all GPUs are imported. In a significant development that can reduce import dependence to a large extent, researchers at IIT Delhi’s Electrical Engineering Department have designed the country’s first working, demonstrable indigenous micro-GPU.
“To the best of our knowledge, this is the first working, demonstrable indigenously designed micro-GPU from a university in India,” the researchers stated.
The micro-GPU architecture developed by IIT Delhi researchers will enable indigenous graphics and display-processing systems for embedded applications.
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The project, led by M Tech students Nammi Akash and M Ravi Teja under the guidance of Jayadeva and Kaushik Saha from the Electrical Engineering Department, IIT Delhi, has demonstrated programmable graphics rendering using a custom floating-point GPU engine implemented entirely in Register Transfer Language (RTL) and mapped to a Spartan-7 Field Programmable Gate Array (FPGA) platform.
The hardware architecture is a scalable programmable graphics processor IP suitable for applications such as industrial control displays, low-cost human-machine interfaces, e-rickshaw dashboard navigators, inland-water navigation terminals for small fishing boats, educational e-book readers, and other affordable embedded visualisation systems. It may be mapped to silicon ASIC or programmable hardware such as FPGAs.
In a joint statement, Akash and Ravi Teja said, “Our objective was to create a compact but genuinely programmable graphics-processing architecture suitable for FPGA implementation and future ASIC realisation. We hope such indigenous hardware systems can support affordable digital-access platforms and contribute meaningfully toward bridging the digital divide. We are grateful to our institute, IIT Delhi, for providing the academic environment and the technical platform that enabled this work.”
The team is now exploring a roadmap towards an 8–16 core vector-style graphics processor architecture with an optimised compiler and graphics software toolchain, along with eventual migration to a proof of concept at a 65nm ASIC process node. The researchers believe that mature semiconductor process nodes such as 65 nm can potentially enable economically viable and practically useful indigenous graphics silicon for embedded systems applications.
Jayadeva from the Electrical Engineering department said the work demonstrates the educational and research potential of indigenous programmable graphics hardware for affordable and socially useful computing platforms and that many innovations were needed to realise the design on a standard FPGA board.
Kaushik Saha, Electrical Engineering dept., added that the project encourages students to integrate arithmetic hardware, programmable architectures, compilers, and embedded systems thinking within a unified framework while also addressing wider societal accessibility challenges.
The team stated that they plan to seek funding support for ASIC development, system integration, and eventual commercialisation of the technology. (ANI)
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